library verilog;
use verilog.vl_types.all;
entity uart_receiver is
    generic(
        sr_idle         : integer := 0;
        sr_rec_start    : integer := 1;
        sr_rec_bit      : integer := 2;
        sr_rec_parity   : integer := 3;
        sr_rec_stop     : integer := 4;
        sr_check_parity : integer := 5;
        sr_rec_prepare  : integer := 6;
        sr_end_bit      : integer := 7;
        sr_ca_lc_parity : integer := 8;
        sr_wait1        : integer := 9;
        sr_push         : integer := 10
    );
    port(
        clk             : in     vl_logic;
        wb_rst_i        : in     vl_logic;
        lcr             : in     vl_logic_vector(7 downto 0);
        rf_pop          : in     vl_logic;
        srx_pad_i       : in     vl_logic;
        enable          : in     vl_logic;
        counter_t       : out    vl_logic_vector(9 downto 0);
        rf_count        : out    vl_logic_vector(4 downto 0);
        rf_data_out     : out    vl_logic_vector(10 downto 0);
        rf_error_bit    : out    vl_logic;
        rf_overrun      : out    vl_logic;
        rx_reset        : in     vl_logic;
        lsr_mask        : in     vl_logic;
        rstate          : out    vl_logic_vector(3 downto 0);
        rf_push_pulse   : out    vl_logic
    );
end uart_receiver;
